A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

A 150-MHz Translinear Phase-Locked Loop

This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode “log-domain” oscillator in a classical PLL topology to obtain these features. The PLL has been fabric...

A Frequency Synthesis of All Digital Phase Locked Loop

All Digital Phase locked loops (ADPLL) plays a major role in System on Chips (SoC). Many EDA tools are used to design such complicated ADPLLs. It operates on two modes such as frequency acquisition mode and phase acquisition mode. Frequency acquisition mode is faster compared to Phase acquisition, hence frequency synthesis is performed. The CMOS technology is used to design such a complex desig...

All-Digital Phase Locked Loop (ADPLL) -A Review

--The All-Digital Phase-Locked Loop (ADPLL) is digital electronic circuit that are used in modern electronic communication systems like frequency synthesizer, modulator/demodulator etc. This paper presents a review of various ADPLL techniques. The range of input frequency of ADPLL is 40 to 98 MHz; the output frequency may be up to 2.92 to 4 GHz range. The components of ADPLL such as phase detec...

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications

Fuzzy logic for digital phase-locked loop filter design

The problem of robust phase-locked loop design has attracted attention for many years, particularly since the advent of the global positioning system. This paper proposes and demonstrates the use of a fuzzy PLL to estimate the time-varying phase of a sinusoidal signal. It is shown via simulation results that fuzzy PLL's offer performance comparable to analytically derived PLL's (e.g. Kalman fil...